Differences

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--- arm:cortex_m0p [2024/02/04 04:16] – [Memory Map] lars
+++ arm:cortex_m0p [2024/02/04 04:29] (current) – [DHCSR - Debug Halting Control and Status Register] lars
@@ Line 84: / Line 84: @@
 ^ bits ^ name ^ description ^
 | 31 - 16 | DBGKEY | must be 0xa05f |
-| 14 - 4 | reserved | |
+| 15 - 4 | reserved | |
+| 3 | C_MASKINTS | 0 = do not mask; 1 = mask PendSV, SysTick and external configurable interrupts |
+| 2 | C_STEP | 0 = single stepping disabled; 1 = single stepping enabled |
+| 1 | C_HALT | 0 = request a halted processor to run; 1 = request a running processor to halt |
+| 0 | C_DEBUGEN | 0 = halting debug disabled; 1 = halting debug enabled |
 read:
 ^ bits ^ name ^ description ^
 | 31 - 26 | reserved | |
+| 25 | S_RESET_ST | 0 = no processor reset since last DHCSR read; 1 = at least one processor reset since last read of DHCSR |
+| 24 | S_RETIRE_ST | 0 = no instruction executed since last read of DHCSR; 1 = at least one instruction executed since last read of DHCSR |
+| 23 - 20 | reserved | |
+| 19 | S_LOOKUP | 0 = no lookup; 1 = processor in unrecoverable exception |
+| 18 | S_SLEEP | 0 = not sleeping; 1 = sleeping|
+| 17 | S_HALT | 0 = not in debug state; 1 = in debug state |
+| 16 | S_REGRDY | 0 = write to DCRDR but transfer is not complete; 1 = the transfer to/from DCRDR is complete |
+| 15 - 4 | reserved | |
+| 3 | C_MASKINTS | 0 = do not mask; 1 = mask PendSV, SysTick and external configurable interrupts |
+| 2 | C_STEP | 0 = single stepping disabled; 1 = single stepping enabled |
+| 1 | C_HALT | 0 = request a halted processor to run; 1 = request a running processor to halt |
+| 0 | C_DEBUGEN | 0 = halting debug disabled; 1 = halting debug enabled |