datasheet:rp2040
Differences
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datasheet:rp2040 [2025/04/16 21:07] – [Clocks] lars | datasheet:rp2040 [2025/07/07 03:21] (current) – [I2C] lars | ||
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===== Peripherals ===== | ===== Peripherals ===== | ||
+ | ==== IRQ ==== | ||
+ | ^ IRQ Number ^ Signal ^ | ||
+ | | 0 | TIMER 0 | | ||
+ | | 1 | TIMER 1 | | ||
+ | | 2 | TIMER 2 | | ||
+ | | 3 | TIMER 3 | | ||
+ | | 4 | PWM WRAP | | ||
+ | | 5 | USB CTRL | | ||
+ | | 6 | XIP | | ||
+ | | 7 | PIO_0 0 | | ||
+ | | 8 | PIO_0 1 | | ||
+ | | 9 | PIO_1 0 | | ||
+ | | 10 | PIO_1 1 | | ||
+ | | 11 | DMA 0 | | ||
+ | | 12 | DMA 1 | | ||
+ | | 13 | IO BANK 0 | | ||
+ | | 14 | IO QSPI | | ||
+ | | 15 | SIO PROC 0 | | ||
+ | | 16 | SIO PROC 1 | | ||
+ | | 17 | CLOCKS | | ||
+ | | 18 | SPI 0 | | ||
+ | | 19 | SPI 1 | | ||
+ | | 20 | UART 0 | | ||
+ | | 21 | UART 1 | | ||
+ | | 22 | ADC FIFO | | ||
+ | | 23 | I2C 0 | | ||
+ | | 24 | I2C 1 | | ||
+ | | 25 | RTC | | ||
==== Clocks ==== | ==== Clocks ==== | ||
+ | |||
+ | **__Sources: | ||
+ | |||
+ | GPCLK0-1 (GPIO Muxing) (External clocks or Relaxation oscillators) | ||
ROSC : Ring Oscillator (1.8 - 12 MHz) | ROSC : Ring Oscillator (1.8 - 12 MHz) | ||
+ | XOSC : Crystal Oscillator (1 - 15 MHz) | ||
+ | |||
+ | System PLL : (from XOSC) | ||
+ | |||
+ | USB-PLL : (from XOSC) | ||
+ | |||
+ | **__Provided clocks:__** | ||
+ | |||
+ | clk_ref = reference clock (runs from ROSC can be switched to XOSC)(Watchdog + Timers) | ||
- | clk_ref | + | clk_sys |
- | clk_sys | + | clk_peri |
- | clk_peri | + | clk_usb = 48 MHz (USB) |
- | clk_usb | + | clk_adc |
- | clk_adc | + | clk_rtc |
- | clk_rtc | + | clk_gpout0-3 |
Line 194: | Line 234: | ||
- When SPI_CTRLR0_INST_L is 0, the XIP instruction field is appended to the end of the address for XIP accesses, rather than prepended to the beginning | - When SPI_CTRLR0_INST_L is 0, the XIP instruction field is appended to the end of the address for XIP accesses, rather than prepended to the beginning | ||
- The reset value of DMARDLR is increased from 0 to 4. The SSI to DMA handshaking on RP2040 requests only single transfers or bursts of four, depending on whether the RX FIFO level has reached DMARDLR, so DMARDLR should not be changed from this value. | - The reset value of DMARDLR is increased from 0 to 4. The SSI to DMA handshaking on RP2040 requests only single transfers or bursts of four, depending on whether the RX FIFO level has reached DMARDLR, so DMARDLR should not be changed from this value. | ||
+ | |||
+ | ==== I2C ==== | ||
+ | |||
+ | |||
+ | Features: | ||
+ | * TX Buffer depth = 16 | ||
+ | * RX Buffer depth = 16 | ||
+ | * max speed = Fast Mode (standard mode = 100kb/s; fast mode = 400 kb/s) | ||
+ | |||
+ | The GPIO pads should be configured for: | ||
+ | * pull-up enabled | ||
+ | * slew rate limited | ||
+ | * schmitt trigger enabled | ||
+ | |||
+ | Speeds: | ||
+ | * SS == standard speed (100 kHz) | ||
+ | * FS == fast speed (400 kHz) | ||
===== abbreviation dictionary ===== | ===== abbreviation dictionary ===== | ||
datasheet/rp2040.1744837633.txt.gz · Last modified: by lars