RP2040
- Memory Map
- Peripherals
  - IRQ
  - Clocks
  - UART
  - GPIO
  - QSPI
  - I2C
- abbreviation dictionary

RP2040

pin function select table 1 2 3

Memory Map

start address	end address	used for	comment
0x00 00 00 00		ROM
0x10 00 00 00		XIP	eXecute In Place
0x11 00 00 00		XIP no alloc
0x12 00 00 00		XIP no cache
0x13 00 00 00		XIP no cache + no alloc
0x14 00 00 00		XIP CTRL
0x15 00 00 00	0x15 00 40 00	XIP SRAM
0x18 00 00 00		XIP SSI
0x20 00 00 00		SRAM
0x20 00 00 00	0x20 04 00 00	SRAM striped	SRAM 0 -3
0x20 04 00 00		SRAM 4
0x20 04 10 00	0x20 04 20 00	SRAM5
0x21 00 00 00		SRAM 0	not striped
0x21 01 00 00		SRAM 1	not striped
0x21 02 00 00		SRAM 2	not striped
0x21 03 00 00		SRAM 3	not striped
0x40 00 00 00		APB Peripherals
0x40 00 00 00		SYSINFO
0x40 00 40 00		SYSCFG
0x40 00 80 00		CLOCKS
0x40 00 c0 00		RESETS
0x40 01 00 00		PSM
0x40 01 40 00		IO BANK0
0x40 01 80 00		IO QSPI
0x40 01 c0 00		PADS BANK0
0x40 02 00 00		PADS QSPI
0x40 02 40 00		XOSC
0x40 02 80 00		PLL_SYS
0x40 02 c0 00		PLL USB
0x40 03 00 00		BUSCTRL
0x40 03 40 00		UART 0
0x40 03 80 00		UART 1
0x40 03 c0 00		SPI 0
0x40 04 00 00		SPI 1
0x40 04 40 00		I2C 0
0x40 04 80 00		I2C 1
0x40 04 c0 00		ADC
0x40 05 00 00		PWM
0x40 05 40 00		TIMER
0x40 05 80 00		WATCHDOG
0x40 05 c0 00		RTC
0x40 06 00 00		ROSC
0x40 06 40 00		Vreg and Chip Reset
0x40 06 80 00
0x40 06 c0 00		TBMAN
0x50 00 00 00		AHB-Lite Peripherals
0x50 00 00 00		DMA
0x50 10 00 00		USB CTRL
0x50 10 00 00		USB CTRL DPRAM
0x50 11 00 00		USB CTRL REGS
0x50 20 00 00		PIO 0
0x50 30 00 00		PIO 1
0x50 40 00 00		XIP AUX
0xd0 00 00 00		IOPORT Registers
0xd0 00 00 00		SIO
0xe0 00 00 00		Cortex-M0+
0xe0 00 00 00		PPB

Peripherals

IRQ

IRQ Number	Signal
0	TIMER 0
1	TIMER 1
2	TIMER 2
3	TIMER 3
4	PWM WRAP
5	USB CTRL
6	XIP
7	PIO_0 0
8	PIO_0 1
9	PIO_1 0
10	PIO_1 1
11	DMA 0
12	DMA 1
13	IO BANK 0
14	IO QSPI
15	SIO PROC 0
16	SIO PROC 1
17	CLOCKS
18	SPI 0
19	SPI 1
20	UART 0
21	UART 1
22	ADC FIFO
23	I2C 0
24	I2C 1
25	RTC

Clocks

Sources:

GPCLK0-1 (GPIO Muxing) (External clocks or Relaxation oscillators)

ROSC : Ring Oscillator (1.8 - 12 MHz)

XOSC : Crystal Oscillator (1 - 15 MHz)

System PLL : (from XOSC)

USB-PLL : (from XOSC)

Provided clocks:

clk_ref = reference clock (runs from ROSC can be switched to XOSC)(Watchdog + Timers)

clk_sys = sytem clock (max 200 MHz) (Processors, Bus fabric, Memories and Memory mapped Registers)

clk_peri = peripheral clock (max 200 MHz) (UART + SPI)

clk_usb = 48 MHz (USB)

clk_adc = 48 MHz (ADC)

clk_rtc = 46875 Hz (RTC)

clk_gpout0-3 = 4 clocks of up to 50 MHz (GPIO Muxing)

UART

clocked by clk_peri. UARTCLK = clk_peri, PCLK = clk_sys

32xFIFO

maximum Baudrate = UARTCLK/16 ( 125MHz → 7.8 MBit/s)

Baudrate	factor	BRDI	BRDF	m	error
115200@125MHz	67.817	67	0.817	52	0.006%

GPIO

Desciption GPIO , SIO

IO_BANK0 : Register

IO_QSPI: Register

PADS_BANK0: Register

PADS_QSPI: Register

SIO: Register

Function select

\	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9
GPIO 0		SPI0 RX	UART0 TX	I2C0 SDA	PWM0 A	SIO	PIO0	PIO1		USB OVCUR DET
GPIO 1		SPI0 CSn	UART0 RX	I2C0 SCL	PWM0 B	SIO	PIO0	PIO1		USB VBUS DET
GPIO 2		SPI0 SCK	UART0 CTS	I2C1 SDA	PWM1 A	SIO	PIO0	PIO1		USB VBUS EN
GPIO 3		SPI0 TX	UART0 RTS	I2C1 SCL	PWM1 B	SIO	PIO0	PIO1		USB OVCUR DET
GPIO 4		SPI0 RX	UART1 TX	I2C0 SDA	PWM2 A	SIO	PIO0	PIO1		USB VBUS DET
GPIO 5		SPI0 CSn	UART1 RX	I2C0 SCL	PWM2 B	SIO	PIO0	PIO1		USB VBUS EN
GPIO 6		SPI0 SCK	UART1 CTS	I2C1 SDA	PWM3 A	SIO	PIO0	PIO1		USB OVCUR DET
GPIO 7		SPI0 TX	UART1 RTS	I2C1 SCL	PWM3 B	SIO	PIO0	PIO1		USB VBUS DET
GPIO 8		SPI1 RX	UART1 TX	I2C0 SDA	PWM4 A	SIO	PIO0	PIO1		USB VBUS EN
GPIO 9		SPI1 CSn	UART1 RX	I2C0 SCL	PWM4 B	SIO	PIO0	PIO1		USB OVCUR DET
GPIO 10		SPI1 SCK	UART1 CTS	I2C1 SDA	PWM5 A	SIO	PIO0	PIO1		USB VBUS DET
GPIO 11		SPI1 TX	UART1 RTS	I2C1 SCL	PWM5 B	SIO	PIO0	PIO1		USB VBUS EN
GPIO 12		SPI1 RX	UART0 TX	I2C0 SDA	PWM6 A	SIO	PIO0	PIO1		USB OVCUR DET
GPIO 13		SPI1 CSn	UART0 RX	I2C0 SCL	PWM6 B	SIO	PIO0	PIO1		USB VBUS DET
GPIO 14		SPI1 SCK	UART0 CTS	I2C1 SDA	PWM7 A	SIO	PIO0	PIO1		USB VBUS EN
GPIO 15		SPI1 TX	UART0 RTS	I2C1 SCL	PWM7 B	SIO	PIO0	PIO1		USB OVCUR DET
GPIO 16		SPI0 RX	UART0 TX	I2C0 SDA	PWM0 A	SIO	PIO0	PIO1		USB VBUS DET
GPIO 17		SPI0 CSn	UART0 RX	I2C0 SCL	PWM0 B	SIO	PIO0	PIO1		USB VBUS EN
GPIO 18		SPI0 SCK	UART0 CTS	I2C1 SDA	PWM1 A	SIO	PIO0	PIO1		USB OVCUR DET
GPIO 19		SPI0 TX	UART0 RTS	I2C1 SCL	PWM1 B	SIO	PIO0	PIO1		USB VBUS DET
GPIO 20		SPI0 RX	UART1 TX	I2C0 SDA	PWM2 A	SIO	PIO0	PIO1	CLOCK GPIN0	USB VBUS EN
GPIO 21		SPI0 CSn	UART1 RX	I2C0 SCL	PWM2 B	SIO	PIO0	PIO1	CLOCK GPOUT0	USB OVCUR DET
GPIO 22		SPI0 SCK	UART1 CTS	I2C1 SDA	PWM3 A	SIO	PIO0	PIO1	CLOCK GPIN1	USB VBUS DET
GPIO 23		SPI0 TX	UART1 RTS	I2C1 SCL	PWM3 B	SIO	PIO0	PIO1	CLOCK GPOUT1	USB VBUS EN
GPIO 24		SPI1 RX	UART1 TX	I2C0 SDA	PWM4 A	SIO	PIO0	PIO1	CLOCK GPOUT2	USB OVCUR DET
GPIO 25		SPI1 CSn	UART1 RX	I2C0 SCL	PWM4 B	SIO	PIO0	PIO1	CLOCK GPOUT3	USB VBUS DET
GPIO 26		SPI1 SCK	UART1 CTS	I2C1 SDA	PWM5 A	SIO	PIO0	PIO1		USB VBUS EN
GPIO 27		SPI1 TX	UART1 RTS	I2C1 SCL	PWM5 B	SIO	PIO0	PIO1		USB OVCUR DET
GPIO 28		SPI1 RX	UART0 TX	I2C0 SDA	PWM6 A	SIO	PIO0	PIO1		USB VBUS DET
GPIO 29		SPI1 CSn	UART0 RX	I2C0 SCL	PWM6 B	SIO	PIO0	PIO1		USB VBUS EN
QSPI_SCK	XIP SCK					SIO
QSPI_CSn	XIP CSn					SIO
QSPI_SD0	XIP SD0					SIO
QSPI_SD1	XIP SD1					SIO
QSPI_SD2	XIP SD2					SIO
QSPI_SD3	XIP SD3					SIO

QSPI

SSI: Description

XIP_SSI: Register

XIP_CTRL: Register

FRF	description
00b	Motorola Serial Peripheral Protocol (SPI)
01b	Texas Instruments Serial Protocol (SSP)
10b	Nationa Semiconductor Microwire
11b	reserved

clock

pclk and sclk are driven from clk_sys

modifications

ss_in_n is tied high

The following modifications were made to the Synopsys DW_apb_ssi hardware:

XIP accesses are byte-swapped, such that the least-addressed byte is in the least-significant position

Note: this only applies to XIP accesses (RP2040 system addresses in the range 0x10000000 to 0x13ffffff), not to direct access to the DW_apb_ssi FIFOs.

When SPI_CTRLR0_INST_L is 0, the XIP instruction field is appended to the end of the address for XIP accesses, rather than prepended to the beginning
The reset value of DMARDLR is increased from 0 to 4. The SSI to DMA handshaking on RP2040 requests only single transfers or bursts of four, depending on whether the RX FIFO level has reached DMARDLR, so DMARDLR should not be changed from this value.

I2C

Features:

TX Buffer depth = 16
RX Buffer depth = 16
max speed = Fast Mode (standard mode = 100kb/s; fast mode = 400 kb/s)

The GPIO pads should be configured for:

pull-up enabled
slew rate limited
schmitt trigger enabled

Speeds:

SS == standard speed (100 kHz)
FS == fast speed (400 kHz)

abbreviation dictionary

abbreviation	long version	comment
FRF	frame format
ROSC	Ring Oscillator
SPI	Motorola Serial Peripheral Interface
SSI	Synchronous Serial Interface	XIP QSPI peripheral
SSP	Texas Instruments Serial Protocol
XIP	EXecute In Place

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