arm:cortex_m0p
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ARM Cortex-M 0+
Memory Map
| start address | end address | used for | comment |
|---|---|---|---|
| 0xE0 00 E0 08 | 0xE0 00 E0 0F | System Control Block | |
| 0xE0 00 E0 10 | 0xE0 00 E0 1F | SysTick | optional |
| 0xE0 00 E0 10 | SYST_CSR | SysTick Control and Status Register | |
| 0xE0 00 E0 14 | SYST_RVR | SysTick Reload Value Register | |
| 0xE0 00 E0 18 | SYST_CVR | SysTick Current Value Register | |
| 0xE0 00 E0 1C | SYST_CALIB | SysTick Calibration Value Register | |
| 0xE0 00 E1 00 | 0xE0 00 E4 EF | Nested Vectored Interrupt Controller | |
| 0xE0 00 E1 00 | NVIC_ISER | Interrupt Set-Enable Register | |
| 0xE0 00 E1 80 | NVIC_ICER | Interrupt Clear-Enable Register | |
| 0xE0 00 E2 00 | NVIC_ISPR | Interrupt Set-Pending Register | |
| 0xE0 00 E2 80 | NVIC_ICPR | Interrupt Clear-Pending Register | |
| 0xE0 00 E4 00 | 0xE0 00 E4 EF | NVIC_IPRO0-7 | Interrupt Priority Registers |
| 0xE0 00 ED 00 | 0xE0 00 ED 3F | System Conrol Block | |
| 0xE0 00 ED 00 | CPUID | ||
| 0xE0 00 ED 04 | ICSR | Interrupt Control and State Register | |
| 0xE0 00 ED 08 | VTOR | optional | |
| 0xE0 00 ED 0C | AIRCR | Application Interrupt and Reset Control Register | |
| 0xE0 00 ED 10 | SCR | System Control Register | |
| 0xE0 00 ED 14 | CCR | Configuration and Control Register | |
| 0xE0 00 ED 1C | SHPR2 | System Handler Priority Register 2 | |
| 0xE0 00 ED 20 | SHPR3 | System Handler Priority Register 3 | |
| 0xE0 00 ED 90 | 0xE0 00 ED b8 | Memory Protection Unit | optional |
| 0xE0 00 EF 00 | 0xE0 00 EF 03 | Nested Vectored Interrupt Controller |
arm/cortex_m0p.1701904946.txt.gz · Last modified: 2023/12/07 00:22 by lars