arm:cortex_m0p
This is an old revision of the document!
ARM Cortex-M 0+
Memory Map
| start address | end address | used for | comment |
|---|---|---|---|
| 0x00 00 00 00 | 0x1f ff ff ff | Code | |
| 0x20 00 00 00 | 0x3f ff ff ff | SRAM | |
| 0x40 00 00 00 | 0x5f ff ff ff | Peripheral | |
| 0x60 00 00 00 | 0x7f ff ff ff | RAM | |
| 0x80 00 00 00 | 0x9f ff ff ff | RAM | |
| 0xa0 00 00 00 | 0xbf ff ff ff | Device | |
| 0xc0 00 00 00 | 0xdf ff ff ff | Device | |
| 0xe0 00 00 00 | 0xff ff ff ff | System | |
| 0xe0 00 00 00 | 0xe0 0f ff ff | PPB | Private Peripheral Bus |
| 0xE0 00 E0 00 | 0xE0 00 EF FF | System Control Space | |
| 0xE0 00 E0 08 | 0xE0 00 E0 0F | System Control Block | |
| 0xE0 00 E0 10 | 0xE0 00 E0 FF | SysTick | optional |
| 0xE0 00 E0 10 | SYST_CSR | SysTick Control and Status Register | |
| 0xE0 00 E0 14 | SYST_RVR | SysTick Reload Value Register | |
| 0xE0 00 E0 18 | SYST_CVR | SysTick Current Value Register | |
| 0xE0 00 E0 1C | SYST_CALIB | SysTick Calibration Value Register | |
| 0xE0 00 E1 00 | 0xE0 00 EC FF | Nested Vectored Interrupt Controller | |
| 0xE0 00 E1 00 | NVIC_ISER | Interrupt Set-Enable Register | |
| 0xE0 00 E1 80 | NVIC_ICER | Interrupt Clear-Enable Register | |
| 0xE0 00 E2 00 | NVIC_ISPR | Interrupt Set-Pending Register | |
| 0xE0 00 E2 80 | NVIC_ICPR | Interrupt Clear-Pending Register | |
| 0xE0 00 E4 00 | 0xE0 00 E4 EF | NVIC_IPRO0-7 | Interrupt Priority Registers |
| 0xE0 00 ED 00 | 0xE0 00 ED 8F | System Conrol Block | |
| 0xE0 00 ED 00 | CPUID | ||
| 0xE0 00 ED 04 | ICSR | Interrupt Control and State Register | |
| 0xE0 00 ED 08 | VTOR | optional | |
| 0xE0 00 ED 0C | AIRCR | Application Interrupt and Reset Control Register | |
| 0xE0 00 ED 10 | SCR | System Control Register | |
| 0xE0 00 ED 14 | CCR | Configuration and Control Register | |
| 0xE0 00 ED 1C | SHPR2 | System Handler Priority Register 2 | |
| 0xE0 00 ED 20 | SHPR3 | System Handler Priority Register 3 | |
| 0xE0 00 ED 90 | 0xE0 00 ED EF | Memory Protection Unit | optional |
| 0xE0 00 ED 90 | MPU_TYPE | ||
| 0xE0 00 ED 94 | MPU_CTRL | MPU Control Register | |
| 0xE0 00 ED 98 | MPU_RNR | MPU Region Number Register | |
| 0xE0 00 ED 9C | MPU_RBAR | MPU Region Base Address Register | |
| 0xE0 00 ED A0 | MPU_RASR | MPU Region Attribute and Size Register | |
| 0xE0 00 ED F0 | 0xE0 00 EE FF | Debug | |
| 0xE0 00 EF 00 | 0xE0 00 EF 03 | Nested Vectored Interrupt Controller | |
| 0xE0 00 EF 90 | 0xE0 00 EF CF | implementation defined | |
| 0xe0 10 00 00 | 0xff ff ff ff | Vendor_SYS |
arm/cortex_m0p.1701907736.txt.gz · Last modified: 2023/12/07 01:08 by lars