technical spec

pin function select table 1 2 3

IO_BANK0 : Register

IO_QSPI: Register

PADS_BANK0: Register

PADS_QSPI: Register

SIO: Register

SSI: Description Register

pclk and sclk are driven from clk_sys

The following modifications were made to the Synopsys DW_apb_ssi hardware:

1. XIP accesses are byte-swapped, such that the least-addressed byte is in the least-significant position

• *Note**: this only applies to XIP accesses (RP2040 system addresses in

the range 0x10000000 to 0x13ffffff), not to direct access to the DW_apb_ssi FIFOs.

1. When SPI_CTRLR0_INST_L is 0, the XIP instruction field is appended to the end of the address for XIP accesses, rather than prepended to the beginning
2. The reset value of DMARDLR is increased from 0 to 4. The SSI to DMA handshaking on RP2040 requests only single transfers or bursts of four, depending on whether the RX FIFO level has reached DMARDLR, so DMARDLR should not be changed from this value.