technical spec

pin function select table 1 2 3

ROSC : Ring Oscillator (1.8 - 12 MHz

clk_ref = reference clock clk_sys = sytem clock (max 133 MHz clk_peri clk_usb = 48 MHz clk_adc = 48 MHz clk_rtc = 46875 Hz

clocked by clk_peri. UARTCLK = clk_peri, PCLK = clk_sys

32xFIFO

maximum Baudrate = UARTCLK/16 ( 125MHz → 7.8 MBit/s)

Desciption GPIO , SIO

IO_BANK0 : Register

IO_QSPI: Register

PADS_BANK0: Register

PADS_QSPI: Register

SIO: Register

SSI: Description

XIP_SSI: Register

XIP_CTRL: Register

pclk and sclk are driven from clk_sys

ss_in_n is tied high

The following modifications were made to the Synopsys DW_apb_ssi hardware:

1. XIP accesses are byte-swapped, such that the least-addressed byte is in the least-significant position

Note: this only applies to XIP accesses (RP2040 system addresses in the range 0x10000000 to 0x13ffffff), not to direct access to the DW_apb_ssi FIFOs.

1. When SPI_CTRLR0_INST_L is 0, the XIP instruction field is appended to the end of the address for XIP accesses, rather than prepended to the beginning
2. The reset value of DMARDLR is increased from 0 to 4. The SSI to DMA handshaking on RP2040 requests only single transfers or bursts of four, depending on whether the RX FIFO level has reached DMARDLR, so DMARDLR should not be changed from this value.