datasheet:rp2040
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Table of Contents
RP2040
pin function select table 1 2 3
| start address | end address | used for | comment |
|---|---|---|---|
| 0x00 00 00 00 | ROM | ||
| 0x10 00 00 00 | XIP | eXecute In Place | |
| 0x11 00 00 00 | XIP no alloc | ||
| 0x12 00 00 00 | XIP no cache | ||
| 0x13 00 00 00 | XIP no cache + no alloc | ||
| 0x14 00 00 00 | XIP CTRL | ||
| 0x15 00 00 00 | 0x15 00 40 00 | XIP SRAM | |
| 0x18 00 00 00 | XIP SSI | ||
| 0x20 00 00 00 | SRAM | ||
| 0x20 00 00 00 | 0x20 04 00 00 | SRAM stripped | SRAM 0 -3 |
| 0x20 04 00 00 | SRAM 4 | ||
| 0x20 04 10 00 | 0x20 04 20 00 | SRAM5 | |
| 0x21 00 00 00 | SRAM 0 | not striped | |
| 0x21 01 00 00 | SRAM 1 | not striped | |
| 0x21 02 00 00 | SRAM 2 | not striped | |
| 0x21 03 00 00 | SRAM 3 | not striped | |
| 0x40 00 00 00 | APB Peripherals | ||
| 0x40 00 00 00 | SYSINFO | ||
| 0x40 00 40 00 | SYSCFG | ||
| 0x40 00 80 00 | CLOCKS | ||
| 0x40 00 c0 00 | RESETS | ||
| 0x40 01 00 00 | PSM | ||
| 0x40 01 40 00 | IO BANK0 | ||
| 0x40 01 80 00 | IO QSPI | ||
| 0x40 01 c0 00 | PADS BANK0 | ||
| 0x40 02 00 00 | PADS QSPI | ||
| 0x40 02 40 00 | XOSC | ||
| 0x40 02 80 00 | PLL_SYS | ||
| 0x40 02 c0 00 | PLL USB | ||
| 0x50 00 00 00 | AHB-Lite Peripherals | ||
| 0xd0 00 00 00 | IOPORT Registers | ||
| 0xe0 00 00 00 | Cortex-M0+ |
Peripherals
Clocks
ROSC : Ring Oscillator (1.8 - 12 MHz
clk_ref = reference clock clk_sys = sytem clock (max 133 MHz clk_peri clk_usb = 48 MHz clk_adc = 48 MHz clk_rtc = 46875 Hz
UART
clocked by clk_peri. UARTCLK = clk_peri, PCLK = clk_sys
32xFIFO
maximum Baudrate = UARTCLK/16 ( 125MHz → 7.8 MBit/s)
| Baudrate | factor | BRDI | BRDF | m | error |
|---|---|---|---|---|---|
| 115200@125MHz | 67.817 | 67 | 0.817 | 52 | 0.006% |
GPIO
QSPI
clock
pclk and sclk are driven from clk_sys
modifications
ss_in_n is tied high
The following modifications were made to the Synopsys DW_apb_ssi hardware:
- XIP accesses are byte-swapped, such that the least-addressed byte is in the least-significant position
Note: this only applies to XIP accesses (RP2040 system addresses in the range 0x10000000 to 0x13ffffff), not to direct access to the DW_apb_ssi FIFOs.
- When SPI_CTRLR0_INST_L is 0, the XIP instruction field is appended to the end of the address for XIP accesses, rather than prepended to the beginning
- The reset value of DMARDLR is increased from 0 to 4. The SSI to DMA handshaking on RP2040 requests only single transfers or bursts of four, depending on whether the RX FIFO level has reached DMARDLR, so DMARDLR should not be changed from this value.
abbreviation dictionary
| abbreviation | long version | comment |
|---|---|---|
| FRF | frame format | |
| ROSC | Ring Oscillator | |
| SPI | Motorola Serial Peripheral Interface | |
| SSI | Synchronous Serial Interface | XIP QSPI peripheral |
| SSP | Texas Instruments Serial Protocol | |
| XIP | EXecute In Place |
datasheet/rp2040.1700435322.txt.gz · Last modified: 2023/11/20 00:08 by lars